This course is a major compulsory course of Electronic Information Engineering. Based on Digital Logic Circuits, through learning this course, the students should master the internal structures about in-system programmable logic device (FPGA / CPLD) and working principles; be familiar with in-system programmable logic device development system and Verilog HDL language; have the basic capacity of using the programmable devices for digital system design; lay the foundation for application in modern electronic technology in the EDA profession. The contains of this course mainly include: Introduction to digital design methodology；Introduction to Verilog HDL；Constructs of Verilog HDL; Deign method of Basic combinational circuits and sequential circuit using Verilog HDL; Levels and Styles of Verilog HDL Digital Design；Structure and Application of CPLD/FPGA.

通过本课程学习，学生能能够熟悉在系统可编程逻辑器件（FPGA/CPLD）的内部结构和工作原理，熟练掌握硬件描述语言，能够运用可编程逻辑器件进行基本数字电路和复杂数字系统的设计、开发、分析测试和验证；掌握可编程逻辑器件集成开发工具Quartus Prime和仿真工具Modelsim，并将其用于基本数字电路和复杂数字系统的仿真分析、时序验证、配置下载和在线调试；具备跨文化交流的语言和书面表达能力，能就数字系统设计中的复杂工程问题，在跨文化背景下进行沟通和交流。

成绩评定：百分制。其中平时成绩占10%；线上成绩占10%；实验占30%；期末占50%。

数字逻辑电路

(1)王金明.数字系统设计与Verilog HDL（第8版）.

(2) Michael D.Ciletti. Advanced Digital Design with the Verilog HDL. Publishing House of Electronics Industry,2005.1

(3) Zainalabedin Navabi.Verilog Digital System Design-RTL Synthesis, Testbench, and Verification, Second Edition, Publishing House of Electronics industry,2007.11

(4)《Advanced Digital Design with the Verilog HDL 》Michael D.Ciletti, PublishingHouse of Electronics industry,2004